1. Field of the Invention
The present invention relates to a logic circuit that processes digital data in voltage levels, and particularly, to a semiconductor integrated logic circuit.
2. Description of the Prior Art
FIG. 1 shows logic circuits L1 to Ln connected to a node P according to a prior art. A digital signal "a" is branched at the node P and simultaneously transferred to the logic circuits. The logic circuits L1 to Ln involve input capacitance values C1 to Cn, respectively, which act as load capacitances on the digital signal "a." In practice, some of the logic circuits L1 to Ln allow a delay in receiving the digital signal "a." Even for such logic circuits, the prior art uniformly allocates minimum capacitance depending on specific design rules or manufacturing processes. As a result, the digital signal "a" is subjected to load capacitance that is unnecessarily large.
Namely, the digital signal "a" is subjected to the minimum input load capacitance, which is determined by manufacturing processes, multiplied by the number of the logic circuits. Even if some of the logic circuits are not required to operate at high speed (high frequency), they are each designed to have load capacitance acting on the signal "a," to hinder the operation speed of the other logic circuits that are required to operate at high speed.
Any conventional semiconductor circuit is unable to have both dynamic and static characteristics. Memories with MOS transistors are classified into dynamic memories and static memories. The dynamic memories use the characteristics of MOS transistors of realizing high impedance and store data by accumulating charge in parasitic capacitors or in designed storage capacitors. The static memories employ feedback circuits to actively store data. FIG. 2 shows a dynamic D flip-flop as an example of the dynamic memories, and FIG. 3 shows a static D flip-flop as an example of the static memories.
The dynamic memories have a simple structure as shown in FIG. 2, and therefore, are capable of operating at high speed. The dynamic memories store data by accumulating charge in capacitors and are unable to keep the data for a long time because of a leakage of charge. The dynamic memories have, therefore, a minimum operation frequency. This restricts the degrees of freedom in the dynamic memory designs. A CMOS circuit, one of the circuit for dynamic memories, consumes power in proportion to an operation frequency, and to reduce the power dissipation, it is desirable to decrease the operation frequency thereof, or to suspend the operation thereof when not urgent or when not needed. Such reduction or suspension of operation is restricted by the minimum operation frequency of the CMOS circuit. Testing a circuit and examining trouble in the course of the research and development of the circuit are restricted by the minimum operation frequency of the circuit. The fact whether the circuit is able to or unable to suspend influences the efficiency of the system development. Since the operation of the dynamic memories is unable to suspend due to the minimum operation frequency, there is a serious problem in finding the cause of a malfunction in the dynamic memories.
The static memories structurally store data. For example, they have feedback circuits to hold data, and therefore, the static memories have no minimum operation frequency. They keep data even if they are stopped, as long as source power is supplied thereto. The static memories, however, are large in size and not suitable for high-speed operation. Compared with the dynamic D flip-flop of FIG. 2, the static D flip-flop of FIG. 3 additionally has partial circuits 1 and 3 for statically storing data, and these partial circuits slow down the operation speed of the flip-flop when they are charged and discharged.
Consequently, an ideal semiconductor integrated circuit is "a dynamic-static circuit" that is capable of operating at high speed without a minimum operation frequency. Namely, it operates dynamically at high speed and statically at low speed. There is, however, no prior art that provides such an ideal circuit. "The dynamic-static circuit" may be usable not only for storing data but also for other purposes. For example, it could be applicable to a logic circuit having a precharger as shown in FIG. 4. This kind of logic circuit accumulates, during a precharge period, charge at each node to indicate a logic value, carries out a logic operation during an evaluation period, inverts the logic value of any node if it is unsuitable, and keeps the logic value of any node if it is suitable. Inverting a logic value is carried out by discharging a corresponding node. However, keeping a logic value is carried out with the use of a dynamic or a static circuit, and there was no "dynamic-static logic circuit" having a precharger. Actually, FIG. 4 shows an example of a dynamic logic circuit according to a prior art. This circuit is incapable of operating dynamically at high speed and statically at low speed.
FIG. 5 shows an exclusive OR (EOR) circuit having pass transistors. This circuit is required to operate at high speed without producing a short current. When inputs A and B are at a source voltage, the voltage of a node "b" is dropped from the source voltage by the threshold voltage V.sub.th of an n-channel MOS transistor. This voltage drop due to the threshold voltage of the pass transistor causes a p-channel MOS transistor of a CMOS inverter 5 to insufficiently turn off, thereby steadily passing a short current. To avoid this problem, another prior art has proposed a circuit of FIG. 6. When the potential at a node "c" exceeds a given voltage, a feedback circuit works to increase the potential of the node "c" to a source voltage, to prevent a short current in a CMOS inverter 7. The feedback circuit, however, prevents inputs A and B from falling down to a ground level, thereby preventing high-speed operation. Hence, we can conclude that there has been no prior art that realizes high-speed operation without producing a steady short current.
As explained above, the prior art that branches a digital signal to plural logic circuits including high-speed and low-speed circuits uniformly allocates input capacitance to each of the high-speed and low-speed logic circuits, so that the digital signal is subjected to the input capacitance multiplied by the number of the logic circuits. This prior art is incapable of improving the operation speed of the high-speed logic circuits because it is unable to reduce load capacitance on those of the high-speed logic circuits that must operate at high speed.
There is no prior art that provides "a dynamic-static circuit" having both dynamic and static characteristics.
There is no prior art that provides a circuit capable of operating at high speed without producing a steady short current.